A 12nm CMOS Rail-to-Rail Auto-Zero Operational Amplifier

Based on a 12nm CMOS process, a low-power, low-offset, input/output rail-to-rail auto-zero operational amplifier is proposed. The operational amplifier dynamically removes the input offset voltage by a time-interleaved auto-zero method. The rail-to-rail input common-mode voltage range and constant input transconductance of the operational amplifier are achieved by complementary differential pairs and a 1:3 current mirror. Low power consumption is achieved by a bias circuit which generates an nA-level PTAT current. Under 0.8 V supply voltage, 25°C, The operational amplifier has an input offset voltage of 2.24 µV (typical corner), an input offset current of 5 pA, an equivalent DC gain of 114.8 dB, an input transconductance variation of 5 %, and a power consumption about 3µW, and the chip area is 0.72mm * 0.99mm excluding PAD.