An Computing-in-Memory SAD Architecture Capable of Realizing High-Precision Computing

This paper describes a computing in memory array based on 10T SRAM cells for realizing the subtraction operation of 8bit inputs with 8bit weights in SAD operations, and it is able to achieve high discharge linearity by improving its discharge and high and low-bit merging methods for 10T SRAM arrays. The design and simulation of the memory array part of this architecture is carried out in 110nm CMOS process with a supply voltage of 1.2 V. The simulation results show that the memory array has good linearity of 99.66%, which is conducive to the realization of high-precision SAD operations in the subsequent CIM system.