FPGA Implementation of a Pipelined XMSS Leaf Accelerator

The eXtended Merkle Signature Scheme (XMSS) is a stateful, hash-based digital signature scheme standardized by the IETF in 2018. Its security relies on properties such as the one-way nature of hash functions, making it less vulnerable to quantum computers. The number of signatures that can be generated with a single XMSS public key depends on the height of the tree, requiring the formation of a large tree for efficient operation, which in turn demands significant computational resources and time. This paper presents an FPGA implementation of the Leaf generation process, a part of the XMSS key generation procedure, using parameters compliant with IETF RFC8391. The circuit was divided into two parts for implementation on the FPGA. By performing the hash computation of a 512-bit message block in one clock cycle, the number of cycles was reduced, and throughput was improved by pipelining the hash modules. As a result, the system operated at 6.45 MHz and generated one Leaf in approximately 21.9 microseconds, achieving a generation speed approximately 20 times faster than in previous studies.