FPGA-oriented Two-phase Bundled-data Circular Self-timed Pipeline

Self-timed pipeline (STP) is an attractive circuit architecture because its local data transfer naturally realizes pipeline-stage-level signal gating and thus leads to high power-performance efficiency. A circular STP can realize not only iterative or recursive operations but also program execution. There exists a circuit configuration and its design procedure that make it possible to implement the circular STP on highly available commercial FPGAs, which provide flexibility at circuit level, by utilizing the standard EDA tool provided by the FPGAs’ vendors; however, the existing configuration is premised on a data transfer manner called four-phase bundled-data, in which main transfer control signals transition four times when a set of data is transferred between adjacent pipeline stages. In this paper, we propose a circuit configuration for two-phase bundled-data manner that makes main transfer control signals transition only twice for transferring a data set and thus potentially leads to a higher throughput. The proposed configuration realizes the circular STP’s basic functions: the merge of two pipelines into one, the branch of one pipeline to two, and the copy and/or erasure of a data set. To make it possible to apply the existing design procedure to the proposed configuration, we reveal intrinsic timing constraints exhaustively and present a timing information acquisition technique for static timing analysis. According to the proposed configuration, we implemented a circular STP on AMD Zynq-7000 FPGA. Based on the implementation, we demonstrate that the proposed configuration requires an approximately 15% larger circuit area and it can achieve the approximately 1.6 times higher maximum pipeline throughput in comparison with the existing four-phase bundled-data version.