Disaggregated Designs: Technology Challenges and Enablers

The unsustainable pace of die-size growth has come up against the reticle limit. The rise in cost per transistor (CPT) is outweighing scaling benefits from advances in generational process technology. These diminishing silicon economies of scale have pushed foundries, EDA companies, and the manufacturing ecosystem to enable chiplet designs. Developments in packaging technology and standardization of die-to-die interfaces provide technology gains offsetting challenges of die sizes and CPT. Standards bodies and IP implementers have risen to the challenge, providing solutions to interface bottlenecks. We examine standards for chiplet and die-to-die interfaces, such as UCIe and the work done in the industry to enable these. Architectural partitions for chiplet implementations and development of reusable components that enable a future chiplet marketplace are considered. The juggernaut for differentiation and disaggregation in the more-than-Moore era continues to build momentum. We examine these trends and recent technology advances, looking at future directions for implementations.