Floating Sampling Technique for CMOS SAR ADC with Large Input Amplitude Tolerance Beyond Supply Voltage

This paper presents a floating sampling technique for CMOS SAR ADCs that tolerates large input amplitude exceeding the supply voltage. A novel switched-capacitor sample-and-hold (S/H) circuit incorporating the proposed floating sampling technique effectively attenuates large input amplitudes within the specified range of low supply voltage SAR ADCs, regardless of the common level of the analog input. A 0.7 V 12-bit SAR ADC with the proposed floating sampling circuit is designed in 65 nm SOTB CMOS technology. Simulated SNDR=63.74 dB, SFDR=79.84 dB and ENOB=10.30 bits are achieved while a sinusoid input Vin_ppd=2.8 V (peak-to-peak voltage of differential input voltage) biased at Vin,CM=1.4 V is sampled at 3 MS/s, including the thermal noise of MOSFETs and capacitors of the proposed SAR ADC. The SPICE simulation results also demonstrate that the dynamic performance of the proposed SAR ADC remains stable even when the input common-mode voltage Vin,CM is varied between 1.2 V and 1.6 V. These results indicate the feasibility and effectiveness of the proposed floating sampling technique in efficiently extending the dynamic range of the low supply voltage SAR ADC.