Research on Key Technologies for Chip Area and Power Optimization in Low-Powered Digital Integrated Circuit

With mobile technology being the norm and the need for more computational power for applications such as AI, simulations and virtual reality, integrated circuit chips are required to be smaller to be more power efficient at the same time be more powerful than its predecessors. This paper aims to discuss and present the techniques and technologies involved in optimizing the power consumption and chip area of low-powered digital integrated circuits. In this paper, the CMOS integrated circuit would be the main focus for discussion. The main discussions would be on the subject of various techniques to improve power efficiency and reduce chip area in a low powered CMOS integrated circuit. The two sources of power consumption and factors that affect it would be identified and solutions to reduce power consumption based on each factor would be brought up. Circuit area optimisation would also be discussed at both the design and manufacture level.