Noise Analysis For Active Element Based Capacitor Multipliers

In this study, comprehensive noise analyses and optimization of two different capacitance multiplier structures have been presented. Capacitor multipliers, essential in low frequency applications due to capacitors’ significant chip area requirement, play a significant role in high precision analog circuits. Noise impacts such filters by reducing the signal to noise ratio (SNR), increasing phase noise, and potentially causing distortion, which is critical in applications requiring high accuracy and stability, such as biomedical instrumentation, communication systems, and precision measurement devices. Therefore, thorough analysis and optimization of filter noise characteristics are essential for reliable operation in sensitive applications. Two capacitor multiplier structures are analyzed: the Multiple Output Voltage Differencing Transconductance Amplifier (MO-VDTA) based and the Multiple Output Current Differencing Transconductance Amplifier (MO-CDTA) based structures. The multiplication factor of the capacitor multiplier in basis of MO-VDTA varies between 120 and 750, depending on the IB value. This variation allows the cutoff frequency of the applied fi lter to change between 2 kH z and 12.4 kHz. The MO-CDTA based structure’s multiplication factor varies between 400 and 1250 by changing the VGS voltage of the external PMOS. This structure has been used in a 2nd order low pass filter, with the cutoff frequency varying between 23.6 kHz and 91 kHz in conjunction with multiplication factor changing. In this respect, comprehensive noise analyses of the filter applications of these two structures have been examined to ensure reliable and efficient operation in sensitive applications.