The nature of silicon PN junction impedance at high frequency

A thorough understanding of the small-signal response of solar cells can reveal intrinsic device characteristics and pave the way for innovations. This study investigates the impedance of crystalline silicon PN junction devices using TCAD simulations, focusing on the impact of frequency, bias voltage, and the presence of a low–high (LH) junction. It is shown that the PN junction exhibits the behavior of a parallel resistor–capacitor circuit ( R C -loop) with fixed element values at low frequencies, but undergoes relaxation in both resistance R j and capacitance C j as frequency increases. Moreover, it is revealed that the addition of a LH junction impacts the impedance by altering R j , C j , and the series resistance R s . Finally, while various publications on solar-cell impedance model the LH junction using an R C -loop, the findings in this study indicate that such a model does not accurately represent the underlying physics. Instead, this approach is likely compensating for the frequency-dependent behavior of R j and C j . • The impedance of PN junction devices is studied through TCAD simulations. • The PN junction impedance can be modeled by a resistor–capacitor circuit. • However, the PN junction resistance and capacitance relax at high frequency. • It is shown how the presence of a low–high junction alters the device impedance. • The low–high junction impedance does not behave like a resistor–capacitor circuit.