FPGA-based reduction in complexity of FFT twiddle factor butterfly with embedded CORDIC module

In conventional FFT, techniques reducing twiddle factor complex multiplication have become a research hotspot topic. CORDIC FFT architecture overcomes the existence of multiplier blocks, which raise hardware complexity costs, increase power consumption, and lower maximum operating clock frequency. An iterative-based CORDIC architecture with a compensated barrel shifting network to provide gain k = 0.6 is proposed. This algorithm substitutes sine and cosine convolution factors with repeated KORDIC convolutions, allowing for reduced ROM. A high-speed FFT processor comprising of twiddle factor WN is replaced with an embedded CORDIC module on FPGA. It is observed that CORDIC FFT eliminates the use of 20 DSP components thereby reducing computational complexity at the maximum achievable speed of 75 MHZ. Output is shown successfully on the Artix7 board with a minimal error of approx. 0.25% and an accuracy of 99.75%. Latency and throughput issues are improved in this. Static power in CORDIC FFT is approximately 114 mw.