FIS: A Programmable Multi-Bit Fault Injection Server for Embedded System

The Fault injection technique is commonly used to intentionally introducing attack on embedded systems, specifically advanced FPGAs and microcontrollers. The FPGA-based embedded system uses SRAM for storage of configuration data. Due to technology scaling and growing complexity in FPGA bit files, multiple-bit upset is a primary threat to FPGAs. These devices are also vulnerable to radiation threats in space environments. To address these issues, this paper proposes burst error modeling and a Fault Injection Server (FIS). FPGA is utilized in the proposed fault injection architecture to efficiently inject Multiple-Bit Upset (MBUs) onto the design's interconnect without altering the value of flip-flops associated with the design path. There is no need to reload the same flops and memory with correct values since their values are unchanged. The Xilinx Zynq-7000 FPGA has been used to evaluate the proposed FIS architecture, and It is able to perform two times faster than existing techniques. The FPGA resource utilization overhead also less as compared to other exiting design but it depends on number of fault injection points used.