Design and Analysis of Binary into Gray code converter using Cadence 180nm Technology

This work involves designing a Binary into Gray code conversion system of an XOR gate constructed from NAND gates. The circuit employs Metal Oxide Semiconductor (CMOS) transistors to prioritize chip size, as CMOS designs are often preferred for their compactness. The Binary into Gray code transformer is beneficial for system designers by facilitating error correction and reducing data errors in Analog to Digital converters, thus aiding in Digital Signal Processing. Power usage and area are standard metrics for very large-scale integrated circuits. In proposed paper, the standard power that is used and area of the Binary into Gray code converter had a NAND gate-based XOR gate have been examined using nano-dimensional MOS transistors with a 180nm channel length technology. The circuit’s verification and functionality have been directed using Cadence Virtuoso software, a leading tool for design and verification across semiconductor process nodes. Compared to various design methodologies, our proposed work excels with a consuming power 20.24 µW and a compact area of 192.6 µm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, significantly outperforming other designs in these metrics, despite a slightly higher delay of 56.8 ps.