Switching Loss Reduction with Commutation Loop Layout Optimization for GaN Devices with Low Output Capacitance

Layout parasitics have a significant influence on the switching performance of wide bandgap semiconductors. Thus, a closer investigation of the layout is worthwhile. Typically, layout procedures only focus on reducing the parasitic inductance. In contrast, the current paper proposes two commutation loop layouts for GaN devices, that additionally considers the parasitic layout capacitances. For gallium nitride (GaN) devices, the device capacitance can be of the same order of magnitude as the parasitic layout capacitance. The proposed layouts result in lower switching losses compared to standard layouts by up to 20 %. The degrees of freedom for the designer are illustrated based on a parametric study. The parasitic layout components are extracted using finite element method (FEM) simulations, and the switching losses are estimated using circuit-level simulation.