FPGA-based Multi-Interface Video Capture System for Hi3559

To overcome the constraints imposed by the Hi3559 processor’s limited general video interfaces and poor device compatibility, a multi-interface video capture system based on field-programmable gate arrays (FPGA) is developed. By employing asynchronous double data rate (DDR) access techniques, a decoding selection module is designed to facilitate the transformation of the four video input formats. This video capture system can accept inputs in the PAL, high-definition multimedia interface (HDMI), Cameralink, and serial digital interface (SDI) formats. It employs an FPGA to decode these inputs and encodes them into the low-voltage differential signaling (LVDS) format for output, allowing seamless data exchange with the Hi3559 processor through the Mobile Industry Processor Interface (MIPI). The experimental results reveal that our system can precisely transcode 720p@30Hz PAL video and 1080p@60Hz Cameralink, HDMI, and SDI videos to the LVDS format which is adapted to the Hi3559 series. Video format conversion using our system is robust, ensuring smooth and uninterrupted video streaming without flickering or frame loss.