Study and Experimental Analysis of FIR Hardware Architecture for Real-time Multimedia Applications

For effective Digital Signal Processing (DSP) processor design, optimizing area, power, and delay is essential to meet the needs of digital signal processing applications. This paper focuses on designing a high-speed Finite Impulse Response (FIR) filter incorporating various Multiply-Accumulate (MAC) units. Compared to the direct form, we assume that the FPGA-based pipelined architecture achieves a 66% reduction in delay. Specifically, using a carry-lookahead adder can reduce delay by 67%, and the Wallace tree multiplier provides significant speed improvements, offering more than a 60% enhancement over conventional and Vedic multipliers. This study aims to create a fast FIR filter using the most efficient arithmetic logic. For this purpose, we design the filter with a MAC unit, utilizing MATLAB for signal processing and Verilog HDL (hardware description language). The design is implemented on a Xilinx Artix-7 FPGA using the AC701 evaluation platform.