Evaluation of a BSIM4 Model at Cryogenic Temperature Using 65 nm Bulk Transistors

In recent years, to facilitate the scalability of quantum computers, a CMOS circuit system working at cryogenic temperatures (Cryo-CMOS) has been intensively researched for qubit control. However, circuit designers have to make a circuit simulation model for Cryo-CMOS because cryogenic temperatures fall beyond the temperature range officially guaranteed by semiconductor manufacturers. In this study, we model nMOS and pMOS transistors fabricated with a 65nm bulk process at 4K using BSIM4 (Berkeley Short-channel IGFET Model). We demonstrate that our model can simulate the rapid increase in threshold voltage and the steepening of the subthreshold slope, which are characteristically observed in cryogenic environments.