A High Linearity V-Band Power Amplifier With Gain Response Shaping Method in 65-nm CMOS

This paper presents a V-band three-stage power amplifier (PA) implemented in 65-nm CMOS technology. A two-way parallel power combiner is used to combine two cascode amplifiers for the enhancement of output power. Neutralizing capacitors are used in the power cell and driver cell to mitigate feedback from the inherent transistor gate-drain parasitic capacitance to improve power gain and increase reverse isolation. In order to improve the output power 1-dB compression point (OP1dB), a gain response shaping method is developed using a Class-C cascode amplifier for the power cell and a Class-A common-source amplifier for the second driver cell. Simulation results show a peak small-signal gain of 18.6 dB and a 3-dB bandwidth of 11.7 GHz (52.8-64.5 GHz). This PA has a saturated output power Psat of 19.8 dBm, an OP1dB of 18.8 dBm, and a peak power-added efficiency (PAE) of 9% at 60 GHz. The compact core occupies an area of 0.201 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, and the DC power consumption is 512.7 mW.