A 40GHz Frequency Doubler with 22-nm CMOS SOI Process

This paper proposes a 40GHz frequency doubler using 22-nm CMOS SOI technology. The frequency doubler circuit consists of a push-push structure multiplier, a band-pass filter (BPF), and a driver amplifier. To further improve the output power and isolation, a cascode structure has been added to the push-push structure. The filter is implemented using a first-order LC circuit. The driver amplifier employs a single-stage common source structure. The input port utilizes a transformer-based balun to achieve the conversion of a single-ended signal to a differential signal and to provide input impedance matching. Compared to injection-locked structures and single-ended structures, the push-push structure offers a wider frequency range and achieves higher fundamental suppression. Simulation results show that when the input signal frequency is 20GHz, the output power of the push-push structure frequency multiplier is 1.55dBm, the fundamental and third harmonic suppression is >40dBc, and fourth harmonic suppression is >30dBc, at an input power of 0dBm.