A 2.5Gb/s CDR-PLL with Improved Phase Detector for Jitter Tolerance Enhancement

We proposed a new Hogge-type phase detector which inserts the T/2 delay into the conventional one in order to reduce the clock jitter. In addition, by inserting a variable delay line, it is possible to adjust the offset of the signal sampling time and optimize jitter tolerance. We confirmed the reduction of the clock jitter in the proposed circuit by the behavioral model simulation. In addition, the circuit simulation was performed to confirm the lock operation of the CDR-PLL. Finally, we fabricated a test chip using a 0.18μm standard CMOS process.