Multicell Upsets in Flip-Flops in Advanced FinFET Nodes

Multicell upsets (MCUs) for single-event (SE) irradiations in static random access memory (SRAM) arrays are the norm in advanced technologies. However, MCU events in register circuits are rare due to increased critical charge (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q_{\text {crit}}$ </tex-math></inline-formula>) and spacing between sensitive nodes compared to SRAM cells. In this work, MCUs in flip-flop (FF)-based register circuits are evaluated in 5- and 3-nm fin field-effect transistor (FinFET) technologies. Irradiation results show an increased contribution of MCUs to the overall event rate and increased MCU cluster size with scaling. MCU cross sections for different threshold voltage options as a function of particle linear-energy transfer (LET) values, supply voltage, and threshold voltage are investigated. Scaling from 5- to 3-nm node results in a significant reduction in minimum LET required to cause MCUs for given test conditions. Technology computer-aided design (TCAD) simulations are used to elucidate underlying factors affecting MCU vulnerability.