In-Situ Critical-Path Replica for Variation-Aware Low-Power Designs with Timing Margin Detection

Timing detection is the first step for a variation-aware circuit to disclose the operating condition and assist in finding the amount of voltage scaling to earn back the wasted power when the circuit runs under conditions better than the worst. To avoid the voltage over-scaling issue with traditional in-situ timing-detection registers and to increase the timing-monitoring accuracy compared to traditional off-site critical-path-replica-based detectors, this work proposes a low-cost in-situ critical-path replica (ISCPR) and ISCPR-based circuits for designs with timing margin detection. We use a 22 nm 54b $\times 54 \mathrm{~b}$ multiplier embedding the ISCPR-based canary circuit as a test vehicle to illustrate the proposed design. Measurement results show that the scaled voltage using the ISCPR-based circuit is only 4.5% larger than the ideal value to achieve 26% power saving for a chip with a process at the fast corner.