An Automated Design Platform for ReRAM-based DNN Accelerators with Hardware-Software Co-exploration

Deep neural networks (DNNs) have gained significant attention due to their powerful feature learning capabilities. Traditional von Neumann architecture faces data transfer bottlenecks between computation and memory, hindering processing efficiency. One of the solutions is to use Resistive Random Access Memory (ReRAM) for realizing Computing-In-Memory (CIM) architectures, enabling rapid Matrix-Vector Multiplication (MVM) operations, thus accelerating DNN computations. While designers could optimize the design using hardware simulation tools before fabrication, manual adjustments are time-consuming. Additionally, the mutual influence between the DNN and hardware architecture further exacerbates the complexity of such designs, particularly for those lacking experience and expertise in the field. In this work, we propose an automation platform that aims to co-design the DNN with the underlying ReRAM-based accelerators through parameter search strategies. A training strategy is also proposed to mitigate the impact of ReRAM variation and Stuck-At-1 (SA1) fault. Simulation results show that our proposed training approach maintains an average accuracy of $89.9 \%$ and $77.9 \%$, under the influence of ReRAM-induced variation and Stuck-At-Fault (SAF), respectively, outperforming ${8 4. 5 \%}$ and ${9. 6 \%}$ offered by MNSIM.