TG-in-DRAM: A Transmission Gate based Full Adder using Multi-row Activation for enhanced Throughput in CIM Architectures

The proposed 1TIC DRAM based Compute-inMemory (CIM) architecture resolves Von-Neumann memory-bottleneck issue that degrades energy consumption and performance in processing neural networks. Majority functions in DRAM cells are implemented by simultaneously activating an odd number of rows. In this paper, we present an in memory based 8-Bit full adder based on majority gate logic along with logic gates such as NAND, NOR and XOR. This work makes the first attempt to harness the unique advantages of Transmission Gate (TG) in implementing complex operations beyond the primitive bitwise Boolean operations. Every DRAM cell is replaced by TG which reduces the voltage drop across FET and thus there is a significant amount of improvement in the figure of merits related to energy. This majority-based 8-bit addition using TG offers significant parallelism and throughput capabilities. We verify the resilience of this in-DRAM computing approach to process variations to ensure its robustness against process variations. Energy analysis of the method reveals a 60.93 times enhancement over conventional read operations in a standard DDR3-1333 interface and 2.94 times enhancement over state-of-the-art methods.