A Comparative Analysis of Middle-of-Line Contact Architectures for Complementary FETs

In this paper, we have investigated various middle-of-line contact architectures applied to monolithic complementary FET inverters and have performed a comparative analysis to assess their respective advantages and limitations. For each scheme, we carried out segmentation analysis of resistance and capacitance, and evaluated the DC performance as well as the power-performance characteristics alongside enhancement strategies. The middle VIA scheme features the lowest capacitance but exhibits inferior AC performance to the conventional structure due to the high resistance of the increased contact region parts and the highly doped silicon. The wrap-around-contact (WAC) structure, and the top metal source/drain (TMS) structure which is formed by increasing the contact depth of the top-placed NMOS, have in common that the external resistance is greatly reduced by enlarging the contact area and shortening the length of the high-resistance power VIA. Despite the trade-off with higher capacitance, AC performances of WAC and TMS are improved by 9.0% and 6.5%, respectively, for the same dynamic power. A sensitivity analysis was also performed to clarify the impact of MOL resistance and capacitance on AC performance. The performance gain when applied only to the drain side is less than 1%, highlighting the importance of minimizing the resistance on the source side. In addition, the segmentation analysis of resistance and capacitance shows that while WAC offers the best inverter performance, TMS provides higher DC performance and lower capacitance for NMOS. A hybrid approach using TMS for NMOS and WAC for PMOS combined with further optimization to reduce capacitance on the drain side, would result in an 11.1% speed improvement or a 22.7% reduction in dynamic power consumption.