A 10-bit Two-Stage Pipeline SAR ADC in 55nm CMOS for Compute-in-Memory Applications

Successive approximation register (SAR) ADCs are commonly used in compute-in-memory (CIM) applications, but their efficiencies are limited by the total capacitor area which exponentially increases with the resolution. Pipelined ADC architectures, on the other hand, can achieve high speed and resolution with a smaller capacitor area, but are seldom explored in CIM applications. In this study, we propose a 10-bit, two-stage pipelined ADC which splits a single high-resolution SAR ADC into two independent sub-ADCs with lower resolutions. The pipelined ADC design is implemented and evaluated on a 55 nm CMOS platform to explore its potential applications in CIM. A single-stage SAR ADC with the same resolution is also designed for comparative analysis. The simulation results suggest that the total power consumption of a two-stage pipeline SAR ADC is significantly lower than that of the single-stage SAR ADC at the same sampling rate. Moreover, the reduced footprint of the pipeline ADC can boost the data throughput of RRAM-based CIM macros.