Research of the Sequential Balancing Algorithm for a Multi-Stage DC Amplification Path

The article presents the results of a study of the efficiency of a balancing algorithm for eliminating the initial offset of a DC amplifier path consisting of three unified stages and having a high gain. Each stage has a built-in microcontroller, where an iterative algorithm for automatic offset compensation with a variable step is implemented. Despite the simplicity of the problem for one stage, such a solution for a multi-stage path is associated with some difficulties. The efficiency and stability of cascaded balancing depends on many factors, including the method of distributing the gain across the entire path, the presence of nonlinearity in the formation of the bias voltage, and the presence of noise in the ADC of the microcontroller used to form the bias feedback. The simulation results show that in order to increase the stability and efficiency of the algorithm, it is necessary to strive for a uniform distribution of gain across the cascades of the path. In this case, the nonlinearity of the bias voltage formation does not lead to instability of the algorithm. It is shown that the use of joint cascade balancing increases its efficiency by an average of 52 dB compared to the option of using balancing only in the first cascade. The algorithm is able to compensate for external offset exceeding the dynamic range of the gain by 75 dB, which is a good result.