GRS: A General RISC-V SIMD Vector Acceleration Processor for Artificial Intelligence Applications
In this paper, we present GRS (General RISC-V SIMD), a 64-bit vector processor based on the RISC-V’s vector extension, for Artificial Intelligence applications. This article proposes an improvement scheme with three characteristics. Firstly, GRS supports the Call Mechanism of Quad Pipelining (CMQP) in certain optimization scenarios to skip certain pipelining levels while performing repetitive or redundant calculations. Secondly, GRS adopts a Lane Self Tuning Technique (LSTT) to match different computational task requirements. Thirdly, GRS adds Logic Operation Capabilities Inside (LOCI) to the vector processing unit to share and reduce the interaction cost of control logic to further improve chip performance. Compared with the advanced vector processor ARA, the energy consumption of GRS has been 1.77 times by using a 28nm CMOS process for evaluation.
Authors
- Tianchun Ye (ORCID: https://orcid.org/0000-0002-2384-9037)
- Zhou Wang (ORCID: https://orcid.org/0000-0001-8526-5136)
- Shushan Qiao (ORCID: https://orcid.org/0000-0002-9102-2111)
- Shaojun Wei
- Jiuren Zhou (ORCID: https://orcid.org/0000-0002-0915-5354)
- Shouyi Yin (ORCID: https://orcid.org/0000-0003-2309-572X)
- Xiaonan Tang (ORCID: https://orcid.org/0000-0003-3467-1059)
- Yang Zhou
- Haochen Du
Institutions
- Xidian University (CN)
- Chinese Academy of Sciences (CN)
- Hong Kong University of Science and Technology (HK)
- Institute of Microelectronics (CN)
- Imperial College London (GB)
- Tsinghua University (CN)
Publication Details
- Published
- 2024-11-07
- DOI
- https://doi.org/10.1109/apccas62602.2024.10808289
- Primary Topic
- CCD and CMOS Imaging Sensors
- Type
- article
- Field-Weighted Citation Impact
- 0.00