Organization of an Automated Design Flow for FPGA and ASIC

This paper addresses the global trend of rising semiconductor manufacturing costs, with a particular focus on the increasing expenses related to integrated circuit development. An analysis of integrated circuits research and development expenses reveals a notable increase in costs over time, prompting the need for optimized design approaches. The research explores modern very large scale integration design techniques, emphasizing the importance of hierarchical design flows, back propagation mechanisms and co-design techniques, based on the hierarchical approach to very large scale integration design, to manage growing complexity. A modular architecture leveraging the Eclipse Theia platform is proposed for an electronic computer-aided design system which automates and optimizes the design process. By automating the design process and leveraging back propagation from later stages, this approach enables iterative refinement of solutions. The implementation yields significant design improvements, underscoring the potential of co-design techniques in reducing development time and costs in hardware development.