Towards Safe and Efficient Analog Circuit Design: Active Learning for Feasibility Region Exploration
Active learning (AL), a machine learning paradigm, allows models to focus on the most informative data points, reducing reliance on extensive labeled data. This is particularly valuable in circuit design, where labeled data is expensive and scarce. By efficiently modeling complex behaviors in analog and RF circuits, AL helps reduce costs, and adapt to varied design scenarios. Traditional AL methods focus on learning efficiency but often fail to distinguish between feasible and infeasible design configurations, crucial for practical applications. We propose a novel safe active learning (SAL) approach, Feasibility-Guided Uncertainty-Weighted Embeddings (FGUE), that enhances learning efficiency by prioritizing data points that are both informative and feasible, thereby reducing the risk of exploring unproductive or infeasible design spaces and ensuring that each iteration contributes effectively to the model’s accuracy and applicability.
Authors
- Chuan-Sheng Foo (ORCID: https://orcid.org/0000-0002-4748-5792)
- Anusha James
- Ashish James (ORCID: https://orcid.org/0000-0002-6623-7831)
- Kiat Seng Yeo (ORCID: https://orcid.org/0000-0002-4524-707X)
- Sezin Kircali Ata (ORCID: https://orcid.org/0000-0002-3004-1204)
- Khin Mi Mi Aung (ORCID: https://orcid.org/0000-0002-5652-3455)
- Zhi Hui Kong (ORCID: https://orcid.org/0009-0008-9776-984X)
- Lile Cai (ORCID: https://orcid.org/0000-0001-8783-0186)
Institutions
- Agency for Science, Technology and Research (SG)
- Singapore University of Technology and Design (SG)
- Institute for Infocomm Research (SG)
Publication Details
- Published
- 2024-11-07
- DOI
- https://doi.org/10.1109/apccas62602.2024.10808909
- Citations
- 1
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 0.49
Funders
- National Research Foundation