Using Python Language Capabilities to Implement Elements of the UVM Methodology in the Task of Modeling a Periodic Signal Source

The article discusses the use of the Python programming language to implement elements of the UVM methodology. The methodology is designed to work in FPGA CAD and uses the System Verilog language. The possibility of replacing the System Verilog language used in UVM with a general-purpose programming language is considered, which allows accelerating the process of modeling digital signal processing systems. The article proposes a modified class hierarchy that reproduces the functionality of the agent component from UVM. An example of generating periodic signals for testing precision phase measurement systems is considered. A model of a software application in Python is developed and a class hierarchy is proposed that uses the property of multiple inheritance to transfer global model parameters within this hierarchy.