Design of High-Speed Multipliers using Counter based 4:2 Compressor with Pre-Processing

Adders and multipliers form the basic building blocks in most of the system designs. Multipliers are widely used in arithmetic and logic units, digital signal processing, audio processing, and image processing applications. Multipliers have complex structures and optimization of multiplier designs plays a vital role in improving the performance parameters like area, power, and delay. The proposed work aims to design compressor-based multipliers using counter logic for power and delay-efficient models. A novel 4:2 counter-based compressor with pre-processing is proposed to design multipliers to improve performance parameters like area power and delay. The proposed designs are synthesized on Cadence Genus with 90nm technology. Experiments carried out reveal that the proposed multipliers save a maximum of 21.71% of area, and 75.63% of power and improve speed by 24.28% over multipliers reported in the literature.