A Transient-Enhanced Dual-Loop Low-Dropout Linear Regulator in 65-nm SOI CMOS With <1-μs Settling Time for 5G Applications

This paper presents design and implementation of a new class of transient-enhanced dual-loop output-capacitorless circuit architecture for low-dropout (LDO) linear regulators. The proposed circuit architecture incorporates two types of negative feedback loops to regulate the varying output voltage and it reduces settling time for overshoot and undershoot of the output voltage effectively. In addition, it saves chip size of the regulator by eliminating the use of any output capacitor. The dual-loop LDO regulator is implemented in an effective silicon area of $147 \mu \mathrm{~m} \times$ $\mathbf{2 4 5} \boldsymbol{\mu m}$ with $65-\mathrm{mm}$ SOI CMOS technology. Transient performance of the manufactured regulator is evaluated quantitatively through measurement of the output voltage across wide ranges of load currents $(0.1 / 1 / 5 / 10 \mathrm{~mA})$ and ambient temperatures (-40 $100{ }^{\circ} \mathrm{C}$). The regulator demonstrates a steady-state output voltage of 1.313 V at $27^{\circ} \mathrm{C}$ under a supply voltage of 1.500 V. It achieves the maximum overshoot/undershoot of $195 / 194 \mathrm{mV}$ and the maximum settling time of $940 / 690 \mathrm{~ns}$ within the aforementioned measuring ranges.