A 4 Bit Segmented Current-Steering Harmonic-Cancelling Digital-to-Analog Converter for High Frequency Sine-Wave Synthesis

Sinusoidal signal generators are critical in various integrated circuit systems, such as mixed-signal BIST applications, RF communication systems, and electrochemical impedance spectroscopy. Digital-to-analog converters, which only need to generate a sinusoidal signal, can be realized using digital harmonic-cancelling sine wave synthesizers (DHSS). The sine wave is obtained by adding weighted and shifted square waves, resulting in a staircase approximation of the sinusoid. However, due to mismatch, the weights have some variation, resulting in decreased performance. Dynamic element matching (DEM) techniques are possible, but existing implementations require a large number of unit elements. This paper presents a segmented harmonic-cancelling digital-to-analog converter (HC-DAC) that achieves comparable performance in terms of signal quality, but with a greatly decreased number of unit elements, thereby lowering the circuit complexity. Implemented in a 180 nm CMOS technology, the 4-bit segmented HC-DAC achieves an SDR of 77 dB at 2 MHz with a power consumption of $254 \mu \mathrm{~W}$ and minimal area usage. Simulation results validate the effectiveness of the proposed design, demonstrating significant performance improvements over existing sine wave synthesizers.