An Efficient On-Chip Storage Solution for CNN Accelerator Based on Self-tuning and Co-scheduling

This paper proposed an efficient on-chip storage solution for Convolution Neural Networks (CNNs) accelerator. It mainly improves hardware utilization by exploring the reconfigurability of the on-chip SRAM. First, an optimization method is proposed for the on-chip memory allocation scheme. The partial sum (PSUM) shares the feature map (FM) buffer according to the input and output FM size. A ring-buffer-based self-tuning storage method is designed to avoid PSUM and FM I/O conflicts. Second, the dataflow of the residual block is optimized based on the coscheduling method to improve the utilization of on-chip memory and reduces off-chip memory access. Third, the workload of CNN major operations, such as any kernel size convolution and pooling, can be mapped to the PE array efficiently, and the adder tree of the PE array can be reused with negligible hardware overhead. A prototype accelerator is taped out in $180-\mathrm{nm}$ COMS technology. It achieves 69.1 GOPS peak throughput and 358 GOPS/W energy efficiency @ 161 mW.