Flattening Power Waveforms by Hamming Distance Converter for Side-channel Attacks

It has been reported that circuit designs for achieving tamper-resistance require significant implementation area overhead. In this paper, we propose novel circuit design approaches utilizing the power consumption of $\mathrm{S}-\mathrm{box}^{-1}$, a decryption-specific circuit unused during encryption, to resist power analysis attacks. Our proposed designs involve adding a small circuit called the Hamming Distance Converter (HDC), which leverages the power consumption of the unused circuit (S-box ${ }^{-1}$) to conceal the power consumption characteristics of the targeted circuit (S-box) against attacks, thereby enhancing tamper-resistance. Evaluation in this paper demonstrates that our proposed designs can achieve tamper-resistance approaching that of the conventional design, WDDL, but at less than half the area overhead.

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Publication Details

Published
2024-11-07
DOI
https://doi.org/10.1109/apccas62602.2024.10808349
Primary Topic
Cryptographic Implementations and Security
Type
article
Field-Weighted Citation Impact
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article

Flattening Power Waveforms by Hamming Distance Converter for Side-channel Attacks

Tomoaki Ukezono, T. Nagatomo, Ryoma Katsube
Cryptographic Implementations and Security
article

Flattening Power Waveforms by Hamming Distance Converter for Side-channel Attacks

Tomoaki Ukezono, T. Nagatomo, Ryoma Katsube
article en

Abstract

It has been reported that circuit designs for achieving tamper-resistance require significant implementation area overhead. In this paper, we propose novel circuit design approaches utilizing the power consumption of $\mathrm{S}-\mathrm{box}^{-1}$, a decryption-specific circuit unused during encryption, to resist power analysis attacks. Our proposed designs involve adding a small circuit called the Hamming Distance Converter (HDC), which leverages the power consumption of the unused circuit (S-box ${ }^{-1}$) to conceal the power consumption characteristics of the targeted circuit (S-box) against attacks, thereby enhancing tamper-resistance. Evaluation in this paper demonstrates that our proposed designs can achieve tamper-resistance approaching that of the conventional design, WDDL, but at less than half the area overhead.

Fukuoka University (JP)
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Cryptographic Implementations and Security
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