Random Clock Gating for Side-channel Protection

In the internet society, side-channel attacks on cryptographic systems have become a significant vulnerability. By exploiting side-channels such as power consumption information during cryptographic processing, secret keys can easily leak. This paper proposes a new circuit design technique to counteract power analysis attacks. We utilize clock gating technology, traditionally used for low-power consumption, for tamper-resistant design. By controlling clock gating with random numbers, we prevent the leakage of secret keys from the power consumption waveforms of the cryptographic system. Our evaluation demonstrates that the proposed random clock gating technique achieves superior tamper-resistance compared to the conventional WDDL countermeasure in FPGA-based attack evaluations, and it can be implemented with relatively minor increases in implementation area overhead.