A Unified Deep Reinforcement Learning Approach for Constructing Rectilinear and Octilinear Steiner Minimum Tree
The Steiner minimum tree (SMT) serves as an optimal connection model for multiterminal nets in very large scale integration (VLSI). Constructing both rectilinear SMT (RSMT) and octilinear SMT (OSMT) are known to be NP-hard problems. Simultaneously, constructing multiple topologies of SMTs for a given net holds significant importance in alleviating routing constraints such as alleviating congestion and ensuring timing convergence. However, existing efforts predominantly focus on designing specialized methods to construct a specifically structured SMT for a given net, making it challenging to extend to different structures or topologies of SMTs, while also exhibiting insufficient optimization capabilities. In this work, we propose a unified approach based on deep reinforcement learning (DRL) to address both RSMT and OSMT problems while generating diverse routing topologies. First, we design an edge point sequence (EPS) that leverages the structural characteristics of SMT to connect the output of the deep learning model with the SMT structure. Second, we propose a deep learning model tailored for EPS, employing the negative wirelength of SMT as a reward to train the model using DRL. Third, we provide a corresponding rapid and accurate wirelength computation algorithm for evaluating the quality of the construction solution to expedite model training. Finally, we leverage the stochastic nature of machine learning to construct diverse SMT construction solutions. To the best of our knowledge, this is the first unified approach capable of simultaneously addressing both RSMT and OSMT problems while generating diverse solutions. The proposed unified approach demonstrates superior solution quality and higher efficiency compared to specifically designed algorithms.
Authors
- Yibo Lin (ORCID: https://orcid.org/0000-0002-0977-2774)
- Xing Huang (ORCID: https://orcid.org/0000-0002-5396-110X)
- Genggeng Liu (ORCID: https://orcid.org/0000-0002-3099-4371)
- Ting-Chi Wang (ORCID: https://orcid.org/0000-0002-3435-0418)
- Jixin Zhang (ORCID: https://orcid.org/0000-0001-6890-8953)
- Zhenkun Lin (ORCID: https://orcid.org/0009-0005-4288-6529)
- Wenhao Liu (ORCID: https://orcid.org/0000-0003-4571-6523)
Institutions
- Nvidia (United Kingdom) (GB)
- Northwestern Polytechnical University (CN)
- Peking University (CN)
- National Tsing Hua University (TW)
- Fraunhofer Institute for Integrated Circuits (DE)
- Hubei University of Technology (CN)
- Fuzhou University (CN)
Publication Details
- Journal
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Published
- 2024-12-27
- DOI
- https://doi.org/10.1109/tcad.2024.3523429
- Citations
- 1
- Primary Topic
- VLSI and FPGA Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.21
Funders
- National Natural Science Foundation of China