SR-BIP: A Soft Error-Resilient Binary Neural Network Inference Processor

This brief presents an efficient binary neural network inference processor, that is, resilient to soft errors caused by potential circuit faults. The proposed processor, SR-BIP, achieves error resilience based on a recompute-based error correction technique. The recompute is selectively performed by exploiting spatial locality inherent in a feature map, to minimize overhead. For the CIFAR10 task at 0.1% bit error rate, SR-BIP achieves 84.42% accuracy, which is 17.59% higher than that without any error resilience. Despite this error resilience, SR-BIP exhibits a resource efficiency of 75.27 MOP/s/LUT in a 28-nm FPGA, which is as high as that of the previous state-of-the-art processor designed without considering error resilience.