Active Gate Driver Design Using Differential Timing-based Miller Detector for Power MOSFET

A low-power active gate driver (AGD) design becomes critical in battery-based power conversion systems (DCDC converters) to extend battery life. This paper proposes an integrated active gate driver with a novel differential timingbased detector that detects very narrow Miller regions effectively and also incorporates the voltage mode power-gating circuit that shuts off $\mathbf{N}-1$ PMOS devices in the $\mathbf{P}$-channel MOS array to reduce power loss. A novel current modulation mechanism is employed to further minimize the redundant static power dissipation that occurs in the comparators during steady-state operation in the detector and power-gating circuit. The proposed AGD achieves a 15% power reduction when tested with a capacitor load of $2 \mathbf{n F}$ and an input PWM signal frequency of 500 kHz using power-gating and current modulation.