Design of a 3rd-Order 12-bit Incremental ADC for Power Monitoring Applications

The incremental ADC is an analog-to-digital converter with high-resolution, high-linearity, and power-efficient properties. It is especially suitable for multi-channel input sensor applications. In this paper, we propose a $3^{\text {rd }}-$ order incremental ADC (IADC) designed for power monitoring applications. The proposed IADC was implemented with switched-capacitor integrators and cascade integrator feed-forward (CIFF) architecture. The design procedures, including high-level macro-model and SPICE-level simulations, are also presented. The proposed incremental ADC has a maximum of 14.7 ENOB while consuming $62.27 \mu \mathrm{~W}$.