Safeguarding the Silicon: Strategies for Integrated Circuit Layout Protection
Modern integrated circuit (IC) production involves a complex supply chain with security risks like Trojans, physical probing or manipulation. We propose DEFense, an extensible computer-aided design (CAD) framework that aims for “security closure” at the physical-layout level, balancing security with traditional power, performance, and area (PPA) goals. DEFense automates vulnerability assessment for IC layouts, guiding CAD tools in adjusting placement, routing, and applying other defense methods. DEFense is offered to the community [1].
Authors
- Jayanth Gopinath
- Johann Knechtel (ORCID: https://orcid.org/0000-0001-5093-2939)
- Ramesh Karri (ORCID: https://orcid.org/0000-0001-7989-5617)
- Ozgur Sinanoglu (ORCID: https://orcid.org/0000-0003-0782-0397)
- Mohammed Ashraf (ORCID: https://orcid.org/0000-0002-1256-7229)
- Jitendra Bhandari (ORCID: https://orcid.org/0000-0003-1017-1690)
Institutions
- New York University (US)
Publication Details
- Published
- 2024-11-07
- DOI
- https://doi.org/10.1109/apccas62602.2024.10808337
- Primary Topic
- Integrated Circuits and Semiconductor Failure Analysis
- Type
- article
- Field-Weighted Citation Impact
- 0.00