Sub-Threshold Delay-Locked Loop with Piecewise Linearization and Time-Mode Proportional-Integral Locking

This paper investigates the inability-to-lock of sub-threshold charge-pump delay-locked loops (CP-DLL). We show inability-to-lock is rooted to the CP-leakage induced drift of the control voltage of the delay line in the idle state of the CP and the exponential delay $\sim$ voltage relation of the delay line. We further show these root causes can be eliminated by replacing the CP and loop filter with an all-digital time-mode proportional-integral realized using a delay-line time-to-digital converter and a bi-directional gated delay line time integrator and linearizing the delay line using a capacitor digital-to-analog converter whose transfer characteristics are the opposite of those of the delay line. The DLL is designed in a TSMC 130 nm 1.2 V CMOS technology with a reduced supply voltage of 0.6 V and analyzed using Spectre with BSIM3 device models. Simulation results demonstrate the DLL is able to lock to a $0 \sim 0.6 \mathrm{~V} 100 \mathrm{kHz} {5 0 \%}$ duty-cycle square-wave timing reference at $\mathrm{FF} /-20^{\circ} \mathrm{C}$, TT/27 °C, and $\mathrm{SS} / 60^{\circ} \mathrm{C}$.