Physical Design of RISC-V based System-on-Chip using OpenLane

Open-source tools for designing integrated circuits are crucial for electrical engineering students. However, more references are necessary to promote the tools to the academic environments. This paper presents design and implementation of a PicoSoC (Pico System-on-Chip) using the OpenLane automated VLSI flow. The PicoSoC comprises several modules, including the PicoRV32 CPU, UART and SPI peripherals, and memory blocks. The design methodology encompasses RTL simulation, macro hardening, core hardening, full-chip hardening, and gatelevel simulation. The results indicate successful physical design and functional verification, demonstrating that the gate-level simulation outputs align with those from RTL simulation. The work is useful for designing the physical layout of digital circuits, SoC architecture development, and also promoting open-source IC design tools in academic environments.