An 80-GHz Phase-Locked Loop for MillimeterWave Application in 40-nm CMOS

An 80-GHz charge-pump phase-locked loop (CP-PLL) for millimeter-wave applications is presented in this paper. To support high-frequency operation, the feedback division chain is composed of two stages of divide-by-2 injection-locked frequency dividers (ILFD), which provide a wide locking range without adding system complexity, followed by a current-mode-logic divider (CMLD), true-single-phase-clock (TSPC) divider and static CMOS dividers. The VCO adopts a class-D current-source-free structure for low-noise consideration. Fabricated in a 40-nm CMOS technology, the implemented CP-PLL operates at $76.7 \mathrm{GHz}-83 \mathrm{GHz}$; the locking range is $7.9 \%$. It consumes 38.3 mW from a $0.9-\mathrm{V}$ supply voltage, and the output power is -2.5 dBm. The phase noise at $1-\mathrm{MHz}$ and $10-\mathrm{MHz}$ offset frequencies are $\mathbf{- 8 2} \mathrm{dBc} / \mathrm{Hz}$ and $-107.2 \mathrm{dBc} / \mathrm{Hz}$, respectively. The circuit achieves a reference spur of -51 dBc. With an integrated jitter of 355 fs, and the FoM-jitter is -233.2. The CP-PLL core area occupies $0.33 \mathrm{~mm}^{2}$.