Proposal and Validation of Annealing-processor-calculation Method Using Error-diffusion Rounded Interaction Matrix

Annealing processors, which are based on an Ising model and specialized for solving combinatorial optimization problems (COPs) have been gaining attention. If the annealing processor calculates at a bit level lower than the value of the Ising model formulation, there is a possibility that COPs cannot be solved. We propose annealing processor calculation method using an error-diffusion rounded interaction matrix to reduce rounding loss. Error-diffusion rounding, which has been mainly used in image compression, is a technique for diffusing the quantization error of each pixel to its surrounding pixels. By adapting this rounding to the interaction matrix, we confirmed that the solutions satisfying the constraints of COPs at lower bit levels improved without reducing solution quality compared with simple-rounded interaction matrix. In a validation using a 512 -spin knapsack problem, the constraint-weight index improved by 114.5 % below 11 bits. The constraint ratio went from 0 to 100% for 7,8, and 9 bits using proposed method. Actual hardware validation using the 512 -spin knapsack problem also showed an improvement of more than 55 % at constraint-weight index.