A Low-Complexity Reconfigurable FFT Processor for Four Data Overlapping Modes

In this paper, a low-complexity reconfigurable FFT processor with four data overlapping modes including $\mathbf{7 5 \%, 5 0 \%, 2 5 \%,}$ and nonoverlapping modes (Mode 1, Mode 2, Mode 3, Mode 4, accordingly) is proposed. Utilizing a new merged four N/4-point FFTs algorithm, the transform computation of the overlapped data can be saved and reused. Configuring the proposed three memory banks to store the different $N / 4$ samples and the commutator connections for each mode of an N-point FFT, the reconfigurability can be attained. From the analyses, the proposed FFT can save computation by 55%, 35%, and 15% with N = 1024 compared with the conventional FFT for $\mathbf{7 5 \%, 5 0 \%}$, and $\mathbf{2 5 \%}$ data overlapping modes, respectively. The proposed work implemented in the TSMC 40nm CMOS process technology shows Mode 1 has the lowest power consumption per FFT by $1.63 \mathrm{~mW} / \mathrm{FFT}$.

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Publication Details

Published
2024-11-07
DOI
https://doi.org/10.1109/apccas62602.2024.10808748
Primary Topic
Embedded Systems Design Techniques
Type
article
Field-Weighted Citation Impact
0.00

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article

A Low-Complexity Reconfigurable FFT Processor for Four Data Overlapping Modes

Shen-Jui Huang, Lan-Da Van, Sau-Gee Chen, Y.-Y. Wang
Embedded Systems Design Techniques
article

A Low-Complexity Reconfigurable FFT Processor for Four Data Overlapping Modes

Shen-Jui Huang, Lan-Da Van, Sau-Gee Chen, Y.-Y. Wang
article en

Abstract

In this paper, a low-complexity reconfigurable FFT processor with four data overlapping modes including $\mathbf{7 5 \%, 5 0 \%, 2 5 \%,}$ and nonoverlapping modes (Mode 1, Mode 2, Mode 3, Mode 4, accordingly) is proposed. Utilizing a new merged four N/4-point FFTs algorithm, the transform computation of the overlapped data can be saved and reused. Configuring the proposed three memory banks to store the different $N / 4$ samples and the commutator connections for each mode of an N-point FFT, the reconfigurability can be attained. From the analyses, the proposed FFT can save computation by 55%, 35%, and 15% with N = 1024 compared with the conventional FFT for $\mathbf{7 5 \%, 5 0 \%}$, and $\mathbf{2 5 \%}$ data overlapping modes, respectively. The proposed work implemented in the TSMC 40nm CMOS process technology shows Mode 1 has the lowest power consumption per FFT by $1.63 \mathrm{~mW} / \mathrm{FFT}$.

National Yang Ming Chiao Tung University (TW)
National Science and Technology Council
Openalex Percentile: Top 74%
Embedded Systems Design Techniques
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A Low-Complexity Reconfigurable FFT Processor for Four Data Overlapping Modes — Shen-Jui Huang, Lan-Da Van, et al. · (2024) | TGRS Research Map | TGRS