A Low-Complexity Reconfigurable FFT Processor for Four Data Overlapping Modes
In this paper, a low-complexity reconfigurable FFT processor with four data overlapping modes including $\mathbf{7 5 \%, 5 0 \%, 2 5 \%,}$ and nonoverlapping modes (Mode 1, Mode 2, Mode 3, Mode 4, accordingly) is proposed. Utilizing a new merged four N/4-point FFTs algorithm, the transform computation of the overlapped data can be saved and reused. Configuring the proposed three memory banks to store the different $N / 4$ samples and the commutator connections for each mode of an N-point FFT, the reconfigurability can be attained. From the analyses, the proposed FFT can save computation by 55%, 35%, and 15% with N = 1024 compared with the conventional FFT for $\mathbf{7 5 \%, 5 0 \%}$, and $\mathbf{2 5 \%}$ data overlapping modes, respectively. The proposed work implemented in the TSMC 40nm CMOS process technology shows Mode 1 has the lowest power consumption per FFT by $1.63 \mathrm{~mW} / \mathrm{FFT}$.
Authors
- Shen-Jui Huang
- Lan-Da Van (ORCID: https://orcid.org/0000-0001-5673-1193)
- Sau-Gee Chen
- Y.-Y. Wang
Institutions
- National Yang Ming Chiao Tung University (TW)
Publication Details
- Published
- 2024-11-07
- DOI
- https://doi.org/10.1109/apccas62602.2024.10808748
- Primary Topic
- Embedded Systems Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Science and Technology Council