Multiple-Loop Analysis and Design for Fast-Transient Capacitor-less LDO with Dual-Path Compensation and Zero-Pole placement in 65-nm CMOS

The main loop transfer function of a low dropout regulator (LDO) reveals the stability of the main loop but lacks explanations for the high-frequency output voltage ringing. This work proposes a multiple-loop small signal analysis on a capacitor-less LDO with Ahuja compensation in two paths, providing design guidelines to achieve a fast transient response with good multiple-loop stability. Zero-pole placement is incorporated to enhance the transient response and fullspectrum power supply rejection (PSR), explained through the transfer function in multiple loops. The proposed design technique is verified in a $65-\mathrm{nm}$ CMOS process with $0.037 \mathrm{~mm}^{2}$ active area. According to the measurement results, the undershoot and overshoot for load transient current of 0 to 15 mA within a 200ps edge time is only 44 and 46 mV respectively. Furthermore, the measured PSR is better than -46dB in a lowfrequency band and -8dB over the whole spectrum under a 15 mA current load with a 200 pF on-chip capacitor.