Design Exploration of In-Situ Error Correction for Multi-Bit Computation-in-Memory Circuits

As computational complexity continues to rise, the effective design of computation-in-memory (CIM) circuits using high-precision embedded non-volatile memory for convolutional neural networks (CNNs) becomes increasingly critical. Errors may arise from factors such as conductance drift. This study specifically aims to develop a simulation framework for in-situ error correction within multi-bit CIM circuits. The focus lies on in-situ error correction methods that enable immediate error detection and rectification during memory or computational operations at the exact location where data processing and storage occur. The main objective is to investigate ways to minimize the impact of these errors on model accuracy. Utilizing this framework, the research delves into hardware errors in CIM, exploring error causes, statistical patterns, and the effects of extreme error values on accuracy. Additionally, this work introduces and delves deeply into clamping as an error correction mechanism. To enhance hardware efficiency and the effectiveness of error correction, particular emphasis is placed on high-bit weights and safeguarding sensitive convolutional layers. Furthermore, establishing appropriate clamping thresholds and employing a well-suited array-based output grouping strategy are essential. These strategies offer clear optimization paths for CNNs in targeted application scenarios.