A 91.7-dB SNDR Discrete-Time Zoom ADC with a 20-kHz BW in 180-nm CMOS

This work presents a discrete-time zoom analog-to-digital converter (ADC) to achieve a 20 kHz bandwidth. The proposed zoom ADC architecture consists of a 5 -bit coarse successive approximation-register (SAR) ADC with a fine third-order delta-sigma modulator (DSM) ADC to achieve a high signal-to-noise and distortion ratio (SNDR). A currentreuse operational transconductance amplifier is applied in the DSM to save analog power. The chopping and data-weighted averaging techniques are used to improve the flicker noise and the DAC linearity, respectively. The prototype ADC was fabricated in 180-nm CMOS. At 6-MS/s, it consumes 1.57 mW from a 1.8-V supply. The measured SNDR and SFDR are 91.7 dB and 106 dB, respectively. The Schreier figure of merit (FoM) is $\mathbf{1 6 2. 7 ~ d B}$.