Pragmatic EDA Flow Runtime Prediction with Machine Learning and Automatic Outlier Removal

As semiconductor process technology advances, the runtimes of electronic design automation (EDA) jobs have become increasingly challenging. At the 3nm process node, for example, a digital circuit design or partition with fewer than 5 million standard cell instances can take 25 days or more to complete the required EDA tasks, which include logic synthesis and physical design flows. To accurately estimate the schedule of a system-on-chip (SoC) design project and to automatically identify EDA jobs having abnormal runtimes, predicting EDA flow runtimes for individual circuit partitions is essential. Although a reinforcement learning (RL)-based approach for EDA flow runtime prediction has been published, its industry adoption is hindered by the difficulty of collecting sufficient training data and the presence of outliers. In this paper, we propose a pragmatic machine learning (ML)-based method for predicting EDA flow runtimes, and the method allows automatic removal of outliers and does not require additional computing resources or EDA tool licenses solely for generating training data. Our experimental results demonstrate that the proposed method predicts runtimes with satisfactory accuracy and is applicable across different SoC design projects. Furthermore, the proposed method outperforms an XGBoost-based approach in terms of cross-design runtime prediction accuracy.